POSSE Day 2

I am tying all the different components for collaboration! There is a light at the end of the tunnel!

This is a test of my Blog!

This is a test!

This is a test!

Test of my blog

Blah! Blah! Blah!

2010 FIFA World Cup South Africa™

long time no see!

It has been more than a year that I have posted here and there are new and exciting things to write about. Then I will start blogging so I will remember what I did!

Started MBA with Management course and attended Linkedin seminar

On Wednesday evening, I started the MBA program at the University of Phoenix Irving Campus. The instructor seems to be a very knowledgeable person and he promotes participation among all students. I think these courses together with the project management will round up my vision of being just an engineer.

In my last position as Analog IP verification lead I was dealing intuitively with different aspects of the material that is covered in these courses. Now I will have a better understanding and a better way to organize my self and help organize the projects that I will be involved in the future.

Since the future is unknown for my yet, University of Phoenix gives me the flexibility to study on a different campus if I need to relocate or even to continue on line. I think that the name of the  school helps, but everything is up to the student to succeed and learn.

Today in the morning I attended a very interesting Linkedin seminar by Dennis O’Hagan. He gave us very good ideas on how to present yourself on Linkedin, how to increase your network and the most important, how to use your network to find either a job or preserve your connections and help other people. Dennis also made the comment that it is useful to maintain your Plaxo profile also, to have an up to date agenda with all your contacts information.

Facebook can be thought as the Linkedin equivalent for informal network. I use Facebook to be in touch with my friends. Before attending this seminar, I already had a profile in all these social networks, but now I have a better understanding on how to combine all of them and try to avoid redundancy and be more efficient. I will be revising my Linkedin profile next week.

Now I have a bunch of articles to read for the MBA, work on an evaluation for Pico Express which is a tool that I used to develop a project for several months and now I need to document my experiences, so others may find it useful.

Today I finished the Cost, Communications and Procurement Module.

Last two classes were very  interesting also!

In “Project Management Communications” we had an overview on how information has to flow back and forth between the Project Manager and the stakeholders, namely engineers, managers, etc. Also it was emphasized that a report at the end of project has to be generated to close activities and it should include a “Lessons Learned” section or better if special session is allocated to review the outcome of the project. Documentation is vital to know exactly where you are and where are you going, also to help you plan future projects.

In “Project Management Procurement” we covered what is commonly know as outsourcing:

• How to determine if outsourcing is the solution.
• How to start the process for companies to offer their services.
• How to determine which contract is the best in terms of risk and benefits.
• How to monitor the outsourcing company progress.

In general, I have seen a lot of similarities to what I was doing in my last position as the Analog IP Verification lead and all the concepts covered in this module, specially since I was working with contractors. I think with the experience that I am obtaining with this series of courses, next time I deal with either a personal project or a project that requires interfacing with a big team, I will have a much better set of skills to look ahead and plan the project.

Next week I start the first MBA program at University of Phoenix. I will let you know how it goes, being an engineer sometimes we are too squared for things that require less structure and are more subjective. Lets see!

Started Program Management Courses at CCCCD

In my last job position as an Analog IP Verification lead, I was in charge of selecting methodologies and EDA tool flows that were the most effective for a particular task, without questioning the designer’s experience and decisions. Also since I was coordinating the efforts that will be realized by contractors, I tried to come with the most structured and documented methodology as I could.

This is one of the reasons I decided to take program management classes not as a curricular career, but mostly as tools of the trade. Since now I have some free time I started with the “Cost, Communication & Procurement Management”.

This is an interesting class where you learn how to budget a project and keep track of expenses and resources. Yesterday we played a game in which you have to complete a certain number of tasks, with limited economic and human resources and the possibility to work overtime, hire contractors and lay off people. Since the game was randomized by dice, it was interesting to see how even that the events are random, you can have an impact or control on the final outcome and the early you take decisions, the best control of the situation you can take.

There are two more classes, I will comment on those at the end of the week!

Resume of Antonio F Mondragon, Ph.D.

DIGITAL ARCHITECTURES / SYSTEMS /
ANALOG & MIXED SIGNAL
DESIGN AND VERIFICATION ENGINEER

antoniofmondragon@ieee.org

Extensive experience in Research and Development from Concept to Silicon. Strong technical skills, starting with a high level of abstraction, system modeling, design, simulation, prototyping and integrated circuit implementation in both digital and analog domains. Proficient in critical design tools and languages for system, digital, analog and mixed mode design and verification.  Highly effective in working with cross-functional / international teams.

TECHNICAL SKILLS

Programming Languages: Matlab, Simulink, Maple, C, C++(basic)
Assembly Language (68000, 80×86, TMS320x2x/5x/6x, 8051, 68HC11, PIC16x/17x).
HDL and Scripting Languages: Verilog, VHDL, Perl, Unix Shell, System-C(basic), Verilog-A (basic).
EDA Tools: Cadence, Modelsim, Analog Circuit Studio, Spectre, Spice, Reliability Tools, SPW, SystemView, Synopsys, Synplicity, Xilinx, Altera, Clearcase, DesignSync, Pico Express, Catapult C.

PROFESSIONAL EXPERIENCE

TEXAS INSTRUMENTS INC, Dallas, TX                          2002-2008

nM Analog Integration, Analog Platform Branch

Analog Intellectual Property (IP) Verification Lead Engineer (2008-2008)

Due to the constant silicon re-spins on Analog IP modules, implemented and led an engineering team that unified the verification methodologies for analog and mixed signal designs.

• Established the methodology and proposed guidelines for analog sub-IP/IP verification, behavioral model qualification and technology re-verification.
• Surveyed the best practices across the group to be incorporated into the methodology.
• Proposed verification flows and tools usage to make more efficient use of human/computing/time resources.
• Heavy use of Cadence tools, Fast-Spice simulators, Statistical simulators, as well as co-simulation.
• Unix shell and Perl scripts usage was incorporated for translation and automation.

Digital Signal Processing Solution R&D Center, Broadband Architectures Group

Long Term Evolution (LTE) Precoder Module Design Engineer (2007- 2008)

For the LTE Precoder used in the transmitter path, specified the high-level architecture followed by complete design and verification.  Project involved the design of a non-power of two Discrete Fourier Transform (DFT) using Electronic System Level (ESL) tools. The objective was to develop a single fixed point C model to directly translate to RTL for simulation, FPGA prototyping and ASIC implementation.

• Proposed Prime Factor Discrete Fourier Transform architecture.
• Modeled the Precoder System using Matlab, including fixed point trade offs analysis and Signal to Quantization Noise Ratio (SQNR) evaluation.
• Designed using C language and Electronic System Level tool (C to Verilog RTL synthesis tool).
• Delivered LTE Precoder module for top level integration and was verified on first pass.
• The complete module was written and verified exclusively using standard ANSI-C from conceptualization to FPGA prototyping and ASIC synthesis. The tool used was Pico Express.

Wimax Transmitter FPGA Module Integration and Verification Lead Engineer (2005- 2007)

Led integration and verification for the Wimax (802.16e) baseband transmitter FPGA module.

• Designed Forward Error Correcting (FEC) Register Transfer Level (RTL) modules
• Block Turbo Decoder, Convolutional Encoder and Turbo Encoder
• Designed MAC to PHY interface RTL module.
• Completed RTL module integration, verification and FPGA laboratory first demonstration in Dec’06.
• Designed and integrated Hybrid Automatic Request (HARQ) manager RTL module.
• Complete transmitter integration and FPGA verification in the laboratory in Aug’07.
• The tools used were Modelsim, Synplicity, Xilinx P&R, Synopsys synthesis.

Digital Television Module RTL Design Engineer (2004- 2005)

Worked across multi-national teams to deliver a first pass silicon single chip digital television integrated circuit.  Team won the “Innovators in Action” award for achievement to go from concept to working silicon in a very short time.

• Designed modules for Digital Video Broadcasting for Handheld (DVB-H/Europe) and Integrated Services Digital Broadcasting Terrestrial (ISDB-T/Japan) standards:
• Time Domain Synchronization (DVB-H/ISDB-T), FFT Bit Reversal (DVB-H/ISDB-T), Post FFT Phase and Gain Adjustment (DVB-H/ISDB-T), Tone Separation and Phase descrambling (ISDB-T) and TMCC Decoder (ISDB-T).
• Configured FPGA synthesis and place and route tool flows for time domain processing.
• Established RTL Power estimation methodology for DVB-H/ISDB-T mixed language design.
• Tools used: Modelsim, Synplicity, Xilinx P&R, Synopsys synthesis.

Digital Signal Processing Solution R&D Center, Mobile Wireless Group

Chip Level Equalizer for 3G Cellular Wireless Module RTL Design Engineer (2002- 2004)

To facilitate integration of a 3G cellular WCDMA chipset, developed a chip level equalizer (CLE) required to deliver the high data rate throughput specified in HSDPA. CLE design resulted in a patent.

• Setup a methodology to generate hardware estimates, and obtained complexity values for both chip level equalizer and interference cancellation.
• Participated in the decision process as to which technique was to be implemented in the first stage of HSDPA coprocessor development.
• Worked through the process of setting the technical specifications for the CLE and started to work on the design from concept to implementation and testing.
• Proposed an innovative CLE Reconfigurable Architecture (submitted patent application).
• Integrated receive and transmit diversity modes into CLE Reconfigurable Architecture and updated the fixed point C model (submitted additional patent with extensions).
• The tools used included Mentor’s HDL Designer series, Synplicity, Xilinx P&R and Synopsys synthesis tools.

ADDITIONAL RELEVANT EXPERIENCE

Communications Systems Development Manager                    PCTV (Mexico City)
R&D Manager in charge of Teletext Products and Operation    TVSCOM (Mexico City)
Teletext Systems Design Engineer                                           TVSCOM (Mexico City)

EDUCATION

Ph.D.  EE  Texas A&M University (College Station, TX, USA)
M.Sc.  EE  Universidad Nacional Autonoma de Mexico (Mexico City, Mexico)
B.Sc.   EE  Universidad Iberoamericana (Mexico City, Mexico)